Semicon India 2026: from promises to packaging

At SEMICON India 2026, Prime Minister Narendra Modi announced that India now has five chip assembly and packaging plants in commercial production, and he launched the second phase of the India Semiconductor Mission, Semicon 2.0, with an outlay of about 13.5 billion dollars, up from about 8 billion dollars in the first phase. The distinction inside that announcement is the whole story. All five plants are back-end units, assembly, test, marking, and packaging lines, not wafer fabrication plants. Packaging a chip in India is real manufacturing, but fabricating the silicon wafer itself is a different level of difficulty, and it has not happened yet.

The five plants trace the year's progress. Micron's Sanand facility in Gujarat began shipping commercial DRAM and NAND memory modules in late 2025, with a formal inauguration in February 2026. Kaynes Semicon's packaging plant became commercially operational in March 2026, and CG Semi's joint-venture outsourced assembly and test unit with Renesas began commercial production in July 2026. At the September 2026 event, Modi virtually inaugurated two more production lines: CDIL Semiconductor in Mohali, Punjab, for discrete devices, and Suchi Semicon in Surat, Gujarat, for packaging. Twelve projects in total have been approved under the first phase.

The harder test is still under construction. Tata Electronics' 300-millimetre fabrication plant at Dholera in Gujarat, built with Taiwan's Powerchip Semiconductor Manufacturing Corporation, is India's first large-scale commercial fab, and commercial-scale output is reported for around 2028, with first wafers targeted for late 2026. Tata also announced a 363-acre vendor park at Dholera for equipment, chemicals, and materials partners. That detail matters, because nearly every fab India is building depends on semiconductor-grade chemicals made mostly in Japan and Germany and production equipment made mostly in the United States, the Netherlands, and Japan.

Semicon 2.0 is designed for that gap. Approved by the Union Cabinet on 15 July 2026 with an outlay of 1,27,500 crore rupees, it rests on six pillars: design, machines and materials, fabs, advanced packaging, applied research, and talent. The government is targeting 200 chip design startups, and officials said about 70,000 design engineers have been trained in four years against an original target of 85,000 over ten years. Investment commitments reported at the summit, including around 1 lakh crore rupees under the ecosystem programme, are commitments rather than money already spent, and should be read that way.